The main objective of this paper was to develop the NoC-AXI Bridge. Its purpose is to enable communication between AXI4-Lite-compatible modules through a network on chip. AXI4-Lite protocol transfers data by means of nineteen signals divided in five channels. Synchronization of the transfer is achieved by using so called VALID/READY handshake process. VALID/READY handshake enables flow control by both parties in a transaction. Through the network on chip, data travels split in many packets. Those packets are called flits. NoC-AXI Bridge consists of two separate adapters. Master Network Adapter --- MNA, and Slave Network Adapter --- SNA. Which of those two will be used depends on a role of the module in an AXI4-Lite transaction. Each adapter consists of two data flows --- Request Flow and Response Flow. The Request Flow transfers read or write requests from the Master to the Slave module, while the Response Flow transfers responses from the Slave to the Master module. Each flow of each adapter consists of multiple modules. The main module of each flow is a finite state machine tasked with synchronizing communication between the adapter and its surroundings. Flows also consist of additional modules that are tasked with formatting data, filtrating data and storing return addresses. Implementation of the NoC-AXI Bridge in Verilog and its testing was approached from the bottom up --- all the modules were individually implemented and tested before the integration. That approach made testing significantly easier. The final stage of the verification process was placing NoC-AXI Bridge in a real environment and connecting it with real AXI4-Lite-compatible modules.